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for more detail ,psl reference MCU4101 Lab 5& 6
//ADC Single
 OpenADC10( ADC_MODULE_ON | ADC_IDLE_CONTINUE | ADC_FORMAT_INTG16 | ADC_CLK_MANUAL | ADC_AUTO_SAMPLING_ON | ADC_SAMP_OFF ,
      ADC_VREF_AVDD_AVSS | ADC_OFFSET_CAL_DISABLE | ADC_SCAN_OFF | ADC_SAMPLES_PER_INT_1 | ADC_ALT_BUF_ON | ADC_ALT_INPUT_OFF ,
      ADC_SAMPLE_TIME_31 | ADC_CONV_CLK_SYSTEM | ADC_CONV_CLK_32Tcy ,
      ENABLE_AN2_ANA , SKIP_SCAN_ALL );
 //ADC_AUTO_SAMPLING_ON(ASAM=1):採樣在上一次轉換結束後執行(the SAMP will be set automatically)
 //ADC_CONV_CLK_SYSTEM:為PB CLK
 //ADC_CLK_MANUAL(SSRC:000):手動觸發 after SAMP be clear(by S/W), then start convert

在PIC32中若要得正確的pb_clk,除了要先填適當的congig bit之外,在程式中亦需執行下列function
// Configure the device for maximum performance but do not change the PBDIV
// Given the options, this function will change the flash wait states, RAM
// wait state and enable prefetch cache but will not change the PBDIV.
// The PBDIV value is already set via the pragma FPBDIV option above..
 SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
or
 SYSTEMConfig(SYS_FEEQ, SYS_CFG_ALL);
or
 SYSTEMConfigPerformance(SYS_FEEQ);
 
 否則peripheral的clk將會錯誤
 
 ex:
 #define SYS_FEEQ 80000000L
 
 int pb_clk;
 pb_clk=SYSTEMConfig(SYS_FEEQ, SYS_CFG_ALL);

這陣子有人問,為什麼 PIC32MX3xx接到ICD2後,都無法連線成功(ICD0042:Error response from MPLAB ICD 2),ICSP的接腳都正確,所有的VDD,GND也都接了,不過在MPLAB "debug"=>setting=>power中,僅VPP有秀出來，其他就為0,
 
在PIC32MX3XX/4XX中, MCU的core是跑1.8v,所以要利用MCU本身的regulator來產生這1.8v的電壓,作法是將ENVREG接至VDD,VDDCORE/VCAP 接一10uf到地, 這樣就可以enable regulator,當然若不想使用內部的regulator,則將ENVREG接至地,VDDCORE/VCAP 接到1.8v vcc.
所有的VDD,VSS,AVDD,AVSS都要接,不然會有error:(如下)
ICD2:
ICD0042: API:  Error response (Device not ready (0x12))
REAL ICE:
RIErr0035: Failed to get Device ID